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| Datasheet File OCR Text: |
| this is information on a product in full production. december 2014 docid15275 rev 14 1/83 stm8l101x1 stm8l101x2 stm8l101x3 8-bit ultra-low power microcontroller with up to 8 kbytes flash, multifunction timers, comparators, usart, spi, i2c datasheet - production data features ? main microcontroller features ? supply voltage range 1.65 v to 3.6 v ? low power consumption (halt: 0.3 a, active-halt: 0.8 a, dynamic run: 150 a/mhz) ? stm8 core with up to 16 cisc mips throughput ? temp. range: -40 to 85 c and 125 c ? memories ? up to 8 kbytes of flash program including up to 2 kbytes of data eeprom ? error correction code (ecc) ? flexible write and read protection modes ? in-application and in-circuit programming ? data eeprom capability ? 1.5 kbytes of static ram ? clock management ? internal 16 mhz rc with fast wakeup time (typ. 4 s) ? internal low consumption 38 khz rc driving both the iwdg and the awu ? reset and supply management ? ultra-low power por/pdr ? three low power modes: wait, active-halt, halt ? interrupt management ? nested interrupt controller with software priority control ? up to 29 external interrupt sources ? i/os ? up to 30 i/os, all mappable on external interrupt vectors ? i/os with programmable input pull-ups, high sink/source capability and one led driver infrared output ? peripherals ? two 16-bit general purpose timers (tim2 and tim3) with up and down counter and 2 channels (used as ic, oc, pwm) ? one 8-bit timer (tim4) with 7-bit prescaler ? infrared remote control (ir) ? independent watchdog ? auto-wakeup unit ? beeper timer with 1, 2 or 4 khz frequencies ? spi synchronous serial interface ? fast i2c multimaster/slave 400 khz ? usart with fractional baud rate generator ? 2 comparators with 4 inputs each ? development support ? hardware single wire interface module (swim) for fast on-chip programming and non intrusive debugging ? in-circuit emulation (ice) ? 96-bit unique id table 1. device summary reference part numbers stm8l101x1 stm8l101f1 stm8l101x2 stm8l101f2, stm8l101g2 stm8l101x3 stm8l101f3, stm8l101g3, stm8l101k3 ufqfpn20 ufqfpn32 tssop20 5 x 5 mm lqfp32 7x7 mm ufqfpn28 4 x 4 mm 3 x 3 mm 6.5 x 6.4 mm www.st.com
contents stm8l101x1 stm8l101x2 stm8l101x3 2/83 docid15275 rev 14 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 single wire data interface (swim) and debug module . . . . . . . . . . . . . . . 10 3.4 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.10 auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.11 general purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.12 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.13 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.14 comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.15 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.16 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.17 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 docid15275 rev 14 3/83 stm8l101x1 stm8l101x2 stm8l101x3 contents 3 9 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3.2 power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 40 9.3.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.7 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3.8 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3.9 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 list of tables stm8l101x1 stm8l101x2 stm8l101x3 4/83 docid15275 rev 14 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8l101xx device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. stm8l101xx pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 5. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. i/o port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. unique id registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. total current consumption and timing in halt and active-halt mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 21. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 22. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 23. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 24. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 25. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. output driving current (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 28. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 29. output driving current (pa0 with high sink led driver capability). . . . . . . . . . . . . . . . . . . . 51 table 30. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 32. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 33. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 34. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 35. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 36. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 37. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 38. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 39. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 40. lqfp32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 68 table 41. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 42. ufqfpn20 - 20-lead ultra thin fine pitch quad flat package (3 x 3 mm) mechanical data . 71 table 43. tssop20 - 20-lead thin shrink small package mechanical data . . . . . . . . . . . . . . . . . . . . 73 table 44. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 docid15275 rev 14 5/83 stm8l101x1 stm8l101x2 stm8l101x3 list of figures 6 list of figures figure 1. stm8l101xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. standard 20-pin ufqfpn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. 20-pin ufqfpn package pinout for stm8l101f1u6atr, STM8L101F2U6ATR and stm8l101f3u6atr part numbers. . . . . . . . . . . . . . . . . . . . . . 15 figure 4. 20-pin tssop package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. standard 28-pin ufqfpn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. 28-pin ufqfpn package pinout for stm8l101g3u6atr and stm8l101g2u6atr part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. idd(run) vs. vdd, fcpu = 2 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12. idd(run) vs. vdd, fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. idd(wait) vs. vdd, fcpu = 2 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14. idd(wait) vs. vdd, fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. typ. idd(halt) vs. vdd, fcpu = 2 mhz and 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. typical hsi frequency vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17. typical hsi accuracy vs. temperature, v dd = 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18. typical hsi accuracy vs. temperature, vdd = 1.65 v to 3.6 v. . . . . . . . . . . . . . . . . . . . . . 46 figure 19. typical lsi rc frequency vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 20. typical vil and vih vs. vdd (high sink i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 21. typical vil and vih vs. vdd (true open drain i/os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 22. typical pull-up resistance r pu vs. v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. typical pull-up current i pu vs. v dd with vin=vss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 24. typ. vol at vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. typ. vol at vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 26. typ. vol at vdd = 3.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 27. typ. vol at vdd = 1.8 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 28. typ. vdd - voh at vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 29. typ. vdd - voh at vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. typical nrst pull-up resistance r pu vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 31. typical nrst pull-up current i pu vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 32. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 33. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 34. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 35. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 36. typical application with i2c bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 37. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 65 figure 38. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 39. lqfp32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 67 figure 40. lqfp32 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 41. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4 mm) . . 69 figure 42. ufqfpn28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 43. ufqfpn20 - 20-lead ultra thin fine pitch quad flat package outline (3x3 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 44. ufqfpn20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 45. tssop20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 list of figures stm8l101x1 stm8l101x2 stm8l101x3 6/83 docid15275 rev 14 figure 46. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 47. stm8l101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 docid15275 rev 14 7/83 stm8l101x1 stm8l101x2 stm8l101x3 introduction 21 1 introduction this datasheet provides the stm8l101x1 stm8l101x2 stm8l101x3 pinout, ordering information, mechanical and electrical device characteristics. for complete information on the stm8l101x1 stm8l101x2 stm8l101x3 microcontroller memory, registers and peripherals, please refer to the stm8l reference manual. the stm8l101x1 stm8l101x2 stm8l101x3devices are members of the stm8l low- power 8-bit family. they are referred to as low-density devices in the stm8l101x1 stm8l101x2 stm8l101x3 microcontroller family reference manual (rm0013) and in the stm8l flash programming manual (pm0054). all devices of the sm8l product line provide the following benefits: ? reduced system cost ? up to 8 kbytes of low-density embedded flash program memory including up to 2 kbytes of data eeprom ? high system integration level with internal clock oscillators and watchdogs. ? smaller battery and cheaper power supplies. ? low power consumption and advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? less than 150 a/mh, 0.8 a in active-halt mode, and 0.3 a in halt mode ? clock gated system and optimized power management ? short development cycles ? application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. ? full documentation and a wide choice of development tools ? product longevity ? advanced core and peripherals made in a state-of-the art technology ? product family operating from 1.65 v to 3.6 v supply description stm8l101x1 stm8l101x2 stm8l101x3 8/83 docid15275 rev 14 2 description the stm8l101x1 stm8l101x2 stm8l101x3 low-power family features the enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application debugging and ultrafast flash programming. all stm8l101xx microcontrollers feature low power low-voltage single-supply program flash memory. the 8-kbyte devices embed data eeprom. the stm8l101xx low power family is based on a generic set of state-of-the-art peripherals. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families including 32-bit families. this makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. all stm8l low power products are based on the same architecture with the same memory mapping and a coherent pinout. table 2. stm8l101xx device feature summary features stm8l101xx flash 2 kbytes of flash program memory 4 kbytes of flash program memory 8 kbytes of flash program memory including up to 2 kbytes of data eeprom ram 1.5 kbytes peripheral functions independent watchdog (iwdg), auto-wakeup unit (awu), beep, serial peripheral interface (spi), inter-integrated circuit (i2c), universal synchronous / asynchronous receiver / transmitter (usart), 2 comparators, infrared (ir) interface timers two 16-bit timers, one 8-bit timer operating voltage 1.65 to 3.6 v operating temperature -40 to +85 c -40 to +85 c or -40 to +125 c packages ufqfpn20 3x3 ufqfpn28 4x 4 ufqfpn20 3x3 tssop20 4.4 x 6.4 ufqfpn28 4x4 ufqfpn20 3x3 ufqfpn32 lqfp32 docid15275 rev 14 9/83 stm8l101x1 stm8l101x2 stm8l101x3 product overview 21 3 product overview figure 1. stm8l101xx device block diagram legend: awu: auto-wakeup unit int. rc: internal rc oscillator i2c: inter-integrated circuit multimaster interface por/pdr: power on reset / power down reset spi: serial peripheral interface swim: single wire interface module usart: universal synchronous / asynchronous receiver / transmitter iwdg: independent watchdog 0 6 9 0 + ] l q w 5 & & o r f n f r q w u r o o h u & o r f n v $ : 8 % h h s h u $ g g u h v v d q g g d w d e x v n + ] l q w 5 & ' h e x j p r g x o h , e & 6 3 , 8 6 $ 5 7 8 s w r . e \ w h v ) o d v k p h p r u \ f r q w u r o o h u . e \ w h v w r f r u h d q g s h u l s k h u d o v , : ' * e l w 7 l p h u 6 : , 0 1 h v w h g l q w h u u x s w x s w r h [ w h u q d o p x o w l p d v w h u e l w 7 l p h u 6 5 $ 0 l q w h u u x s w v l q f o x g l q j x s w r . e \ w h v g d w d ( ( 3 5 2 0 3 r z h u 9 r o w u h j 1 5 6 7 3 2 5 3 ' 5 5 h v h w & 2 0 3 & 2 0 3 3 r u w $ 3 r u w % 3 r u w & 3 r u w ' 5 ; 7 ; & . 6 ' $ 6 & / 3 $ > @ 3 % > @ 3 & > @ 3 ' > @ 0 2 6 , 0 , 6 2 6 & . 1 6 6 % ( ( 3 6 : , 0 & 2 0 3 b & + > @ & 2 0 3 b 5 ( ) , q i u d u h g l q w h u i d f h , 5 b 7 , 0 e l w 7 l p h u 7 , 0 b & + > @ 7 , 0 b & + > @ 7 , 0 b 7 5 , * 7 , 0 b 7 5 , * & 2 0 3 b & + > @ 9 ' ' # 9 ' ' 6 7 0 & r u h x s w r 0 + ] 9 ' ' 9 w r 9 9 6 6 product overview stm8l101x1 stm8l101x2 stm8l101x3 10/83 docid15275 rev 14 3.1 central processing unit stm8 the 8-bit stm8 core is designed for code efficiency and performance. it features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions. 3.2 development tools development tools for the stm8 microcontrollers include: ? the stice emulation system offering tracing and code profiling ? the stvd high-level language debugger including c compiler, assembler and integrated development environment ? the stvp flash programming software the stm8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 3.3 single wire data interface (swim) and debug module the debug module with its single wire data interface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, also cpu operation can be monitored in real- time by means of shadow registers. 3.4 interrupt controller the stm8l101xx features a nested vectored interrupt controller: ? nested interrupts with 3 software priority levels ? 26 interrupt vectors with hardware priority ? up to 29 external interrupt sources on 10 vectors ? trap and reset interrupts docid15275 rev 14 11/83 stm8l101x1 stm8l101x2 stm8l101x3 product overview 21 3.5 memory the stm8l101xx devices have the following main features: ? 1.5 kbytes of ram ? the eeprom is divided into two memory arrays (see the stm8l reference manual for details on the memory mapping): ? up to 8 kbytes of low-density embedded flash program including up to 2 kbytes of data eeprom. data eeprom and flash program areas can be write protected independently by using the memory access security mechanism (mass). ? 64 option bytes (one block) of which 5 bytes are already used for the device. error correction code is implemented on the eeprom. 3.6 low power modes to minimize power consumption, the product features three low power modes: ? wait mode: cpu clock stopped, selected peripherals at full clock speed. ? active-halt mode: cpu and peripheral clocks are stopped. the programmable wakeup time is controlled by the awu unit. ? halt mode: cpu and peripheral clocks are stopped, the device remains powered on. the ram content is preserved. wakeup is triggered by an external interrupt. 3.7 voltage regulators the stm8l101xx embeds an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: main voltage regulator mode (mvr) and low power voltage regulator mode (lpvr). when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in order to reduce current consumption. 3.8 clock control the stm8l101xx embeds a robust clock controller. it is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. this system clock is a 16-mhz high speed internal rc oscillator (hsi rc), followed by a programmable prescaler. in addition, a 38 khz low speed internal rc oscillator is used by the independent watchdog (iwdg) and auto-wakeup unit (awu). 3.9 independent watchdog the independent watchdog (iwdg) peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 38 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure. product overview stm8l101x1 stm8l101x2 stm8l101x3 12/83 docid15275 rev 14 3.10 auto-wakeup counter the auto-wakeup (awu) counter is used to wakeup the device from active-halt mode. 3.11 general purpose and basic timers stm8l101xx devices contain two 16-bit general purpose timers (tim2 and tim3) and one 8-bit basic timer (tim4). 16-bit general purpose timers the 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. they perform a wide range of functions, including: ? time base generation ? measuring the pulse lengths of input signals (input capture) ? generating output waveforms (output compare, pwm and one pulse mode) ? interrupt capability on various events (capture, compare, overflow, break, trigger) 8-bit basic timer the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase generation with interrupt generation on timer overflow. 3.12 beeper the stm8l101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 khz when the lsi clock is operating at a frequency of 38 khz. 3.13 infrared (ir) interface the stm8l101xx devices contain an infrared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. 3.14 comparators the stm8l101xx features two zero-crossing comparators (comp1 and comp2) sharing the same current bias and voltage reference. the voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage). each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. their polarity can be inverted. docid15275 rev 14 13/83 stm8l101x1 stm8l101x2 stm8l101x3 product overview 21 3.15 usart the usart interface (usart) allows full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. 3.16 spi the serial peripheral interface (spi) provides half/ full duplex synchronous serial communication with external devices. it can be configured as the master and in this case it provides the communication clock (sck) to the external slave device. the interface can also operate in multi-master configuration. 3.17 i2c the inter-integrated circuit ( i2c ) bus interface is designed to serve as an interface between the microcontroller and the serial i 2 c bus. it provides multi-master capability, and controls all i2c bus-specific sequencing, protocol, arbitration and timing. it manages standard and fast speed modes. pin description stm8l101x1 stm8l101x2 stm8l101x3 14/83 docid15275 rev 14 4 pin description figure 2. standard 20-pin ufqfpn package pinout 1. hs corresponds to 20 ma high sink/source capability. 2. high sink led driver capability available on pa0. refer to the description of the ir_cr register in the stm8l reference manual (rm0013). note: the comp_ref pin is not available in this standard 20-pin ufqfpn package. it is available on port a6 in the 20-pin ufqfpn package pinout for stm8l101f1u6atr, STM8L101F2U6ATR and stm8l101f3u6atr part numbers ( figure 3 on page 15 ). 0 6 9 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 & 3 & 3 ' + 6 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 $ + 6 3 $ + 6 1 5 6 7 3 $ + 6 9 6 6 9 ' ' 3 & + 6 3 & + 6 3 & + 6 3 $ + 6 docid15275 rev 14 15/83 stm8l101x1 stm8l101x2 stm8l101x3 pin description 21 figure 3. 20-pin ufqfpn package pinout for stm8l101f1u6atr, STM8L101F2U6ATR and stm8l101f3u6atr part numbers 1. please refer to the warning below. 2. hs corresponds to 20 ma high sink/source capability. 3. high sink led driver capability available on pa0. refer to the description of the ir_cr register in the stm8l reference manual (rm0013). warning: for the stm8l101f1u6atr, STM8L101F2U6ATR and stm8l101f3u6atr part numbers (devices with comp_ref pin), all ports available on 32-pin packages must be considered as active ports. to avoid spurious effects, you have to configure them as input pull-up. a small increase in consumption (typ. < 300 a) may occur during the power up and reset phase until these ports are properly configured. 0 6 9 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 & 3 & 3 ' + 6 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 $ + 6 3 $ + 6 1 5 6 7 3 $ + 6 9 6 6 9 ' ' 3 & + 6 3 & + 6 3 & + 6 3 $ + 6 pin description stm8l101x1 stm8l101x2 stm8l101x3 16/83 docid15275 rev 14 figure 4. 20-pin tssop package pinout 1. hs corresponds to 20 ma high sink/source capability. 2. high sink led driver capability available on pa0. refer to the description of the ir_cr register in the stm8l reference manual (rm0013). figure 5. standard 28-pin ufqfpn package pinout 1. hs corresponds to 20 ma high sink/source capability. 2. high sink led driver capability available on pa0. refer to the description of the ir_cr register in the stm8l reference manual (rm0013). note: the comp_ref pin is not available in this standard 28-pin ufqfpn package. it is available on port a6 in the 28-pin ufqfpn package pinout for stm8l101g3u6atr and stm8l101g2u6atr part numbers ( figure 6 on page 17 ). 0 ! ( 3 0 ! ( 3 . 2 3 4 0 ! ( 3 0 ! ( 3 0 # ( 3 6 3 3 0 # ( 3 0 # 0 # 0 " 0 " ( 3 0 " ( 3 0 " ( 3 0 " ( 3 0 " ( 3 0 " ( 3 6 $ $ 0 $ ( 3 0 " ( 3 0 # ( 3 0 6 9 0 6 9 3 ' + 6 3 % + 6 3 % + 6 3 % + 6 3 ' + 6 3 ' + 6 3 ' + 6 3 $ + 6 1 5 6 7 3 $ + 6 3 $ + 6 3 $ + 6 3 $ + 6 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 & 3 ' + 6 3 % + 6 3 & + 6 3 & + 6 3 & + 6 3 & 3 $ + 6 3 & + 6 3 & + 6 9 6 6 9 ' ' docid15275 rev 14 17/83 stm8l101x1 stm8l101x2 stm8l101x3 pin description 21 figure 6. 28-pin ufqfpn package pinout for stm8l101g3u6atr and stm8l101g2u6atr part numbers 1. hs corresponds to 20 ma high sink/source capability. 2. high sink led driver capability available on pa0. refer to the description of the ir_cr register in the stm8l reference manual (rm0013). warning: for the stm8l101g3u6atr and stm8l101g2u6atr part numbers (devices with comp_ref pin), all ports available on 32-pin packages must be considered as active ports. to avoid spurious effects, you have to configure them as input pull-up. a small increase in consumption (typ. < 300 a) may occur during the power up and reset phase until these ports are properly configured. 0 6 9 3 ' + 6 3 % + 6 3 % + 6 3 % + 6 3 ' + 6 3 ' + 6 3 ' + 6 3 $ + 6 1 5 6 7 3 $ + 6 3 $ + 6 3 $ + 6 3 $ + 6 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 & 3 ' + 6 3 % + 6 3 & + 6 3 & + 6 3 & + 6 3 & 3 $ + 6 3 & + 6 3 & + 6 9 6 6 9 ' ' pin description stm8l101x1 stm8l101x2 stm8l101x3 18/83 docid15275 rev 14 figure 7. 32-pin package pinout 1. example given for the ufqfpn32 package. the pinout is the same for the lqfp32 package. 2. hs corresponds to 20 ma high sink/source capability. 3. high sink led driver capability available on pa0. refer to the description of the ir_cr register in the stm8l reference manual (rm0013). 0 6 9 3 ' + 6 3 ' + 6 3 % + 6 3 % + 6 3 % + 6 3 ' + 6 3 ' + 6 3 % + 6 3 $ + 6 3 $ + 6 1 5 6 7 3 $ + 6 3 $ + 6 3 $ + 6 3 $ + 6 3 ' + 6 3 ' + 6 3 ' + 6 3 % + 6 3 % + 6 3 % + 6 3 % + 6 3 ' + 6 3 & 3 & 3 & + 6 3 & + 6 3 & + 6 3 $ + 6 3 & + 6 3 & + 6 9 6 6 9 ' ' docid15275 rev 14 19/83 stm8l101x1 stm8l101x2 stm8l101x3 pin description 21 table 3. legend/abbreviation for table 4 type i= input, o = output, s = power supply level input cm = cmos output hs = high sink/source (20 ma) port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). table 4. stm8l101xx pin description pin number pin name type input output main function (after reset) alternate function standard ufqfpn20 ufqfpn20 with comp_ref (1) tssop20 standard ufqfpn28 ufqfpn28 with comp_ref (1) ufqfpn32 or lqfp32 floating wpu ext. interrupt high sink/source od pp 1 1 4111 nrst/pa1 (2) i/o x hs x reset pa1 2 2 5222pa2 i/o x xxhsxx port a2 3 - 6333pa3 i/o x xxhsxx port a3 - - - 444p a4/tim2_bkin i/o x xxhsxx port a4 timer 2 - break input - - - 5 - 5 pa5/tim3_bkin i/o x xxhsxx port a5 timer 3 - break input - 3 - - 5 6 pa6/comp_ref i/o x xxhsxx port a6 comparator external reference 4 4 7667v ss s ground 5 5 8778v dd s power supply 6 6 9889 pd0/tim3_ch2/ comp1_ch3 i/o x xxhsxx port d0 timer 3 - channel 2 / comparator 1 - channel 3 - - - 9910 pd1/tim3_etr/ comp1_ch4 i/o x xxhsxx port d1 timer 3 - trigger / comparator 1 - channel 4 - - - 101011 pd2/ comp2_ch3 i/o x xxhsxx port d2 comparator 2 - channel 3 - - - 111112 pd3/ comp2_ch4 i/o x xxhsxx port d3 comparator 2 - channel 4 pin description stm8l101x1 stm8l101x2 stm8l101x3 20/83 docid15275 rev 14 7 7 10 12 12 13 pb0/tim2_ch1/ comp1_ch1 (3) i/o x (3) x (3) xhsx x port b0 timer 2 - channel 1 / comparator 1 - channel 1 8 8 11 13 13 14 pb1/tim3_ch1/ comp1_ch2 i/o x xxhsxx port b1 timer 3 - channel 1 / comparator 1 - channel 2 9 9 12 14 14 15 pb2/ tim2_ch2/ comp2_ch1/ i/o x xxhsxx port b2 timer 2 - channel 2 / comparator 2 - channel 1 10 10 13 15 15 16 pb3/tim2_etr/ comp2_ch2 i/o x xxhsxx port b3 timer 2 - trigger / comparator 2 - channel 2 11 11 14 16 16 17 pb4/spi_nss (3) i/o x (3) x (3) xhsx x port b4 spi master/slave select 12 12 15 17 17 18 pb5/spi_sck i/o x xxhsxx port b5 spi clock 13 13 16 18 18 19 pb6/spi_mosi i/o x xxhsxx port b6 spi master out/ slave in 14 14 17 19 19 20 pb7/spi_miso i/o x xxhsxx port b7 spi master in/ slave out - - - 20 20 21 pd4 i/o x xxhsxx port d4 - - ---22pd5 i/o x xxhsxx port d5 - - ---23pd6 i/o x xxhsxx port d6 - - ---24pd7 i/o x xxhsxx port d7 15 15 18 21 21 25 pc0/i2c_sda i/o x xt (4) port c0 i2c data 16 16 19 22 22 26 pc1/i2c_scl i/o x xt (4) port c1 i2c clock 17 17 20 23 23 27 pc2/usart_rx i/o x xxhsxx port c2 usart receive 18 18 1 24 24 28 pc3/usart_tx i/o x xxhsxx port c3 usart transmit 19 19 2 25 25 29 pc4/usart_ck/ cco i/o x xxhsxx port c4 usart synchronous clock / configurable clock output table 4. stm8l101xx pin description (continued) pin number pin name type input output main function (after reset) alternate function standard ufqfpn20 ufqfpn20 with comp_ref (1) tssop20 standard ufqfpn28 ufqfpn28 with comp_ref (1) ufqfpn32 or lqfp32 floating wpu ext. interrupt high sink/source od pp docid15275 rev 14 21/83 stm8l101x1 stm8l101x2 stm8l101x3 pin description 21 warning: for the stm8l101f1u6atr, STM8L101F2U6ATR, stm8l101f3u6atr, stm8l101g2u6atr and stm8l101g3u6atr part numbers (devices with comp_ref pin), all ports available on 32-pin packages must be considered as active ports. to avoid spurious effects, you have to configure them as input pull-up. a small increase in consumption (typ. < 300 a) may occur during the power up and reset phase until these ports are properly configured. - - - 26 26 30 pc5 i/o x xxhsxx port c5 - - - 27 27 31 pc6 i/o x xxhsxx port c6 20 20 3 28 28 32 pa0 (5) /swim/ beep/ir_tim (6) i/o x x (5) xhs (6) xx port a0 swim input and output /beep output/timer infrared output 1. please refer to the warning below. 2. at power-up, the pa1/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa1), it can be configured only as a general purpose pin (pa1), it can be configured only as output push-pull, not neither as output open- drain nor as a general purpose input. refer to section configuring nrst/pa1 pin as general purpose output in the stm8l reference manual (rm0013). 3. a pull-up is applied to pb0 and pb4 during the reset phase. these two pins are input floating after reset release. 4. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer, weak pull-up and protection diode to v dd are not implemented). 5. the pa0 pin is in input pull-up during the reset phase and after reset release. 6. high sink led driver capability available on pa0. slope control of all gpio pins can be programmed except true open drain pins and by default is limited to 2 mhz. table 4. stm8l101xx pin description (continued) pin number pin name type input output main function (after reset) alternate function standard ufqfpn20 ufqfpn20 with comp_ref (1) tssop20 standard ufqfpn28 ufqfpn28 with comp_ref (1) ufqfpn32 or lqfp32 floating wpu ext. interrupt high sink/source od pp memory and register map stm8l101x1 stm8l101x2 stm8l101x3 22/83 docid15275 rev 14 5 memory and register map figure 8. memory map 1. table 5 lists the boundary addresses for each memory size. the top of the stack is at the ram end address. 2. refer to table 7 for an overview of hardware register mapping, to table 6 for details on i/o port hardware registers, and to table 8 for information on cpu/swim/debug module controller registers. * 3 , 2 d q g s h u l s k h u d o u h j l v w h u v [ 5 h v h u y h g ) o d v k s u r j u d p p h p r u \ x s w r . e \ w h v , q w h u u x s w y h f w r u v [ [ ) ) 5 $ 0 [ ) ) . e \ w h v x s w r e \ w h v [ 2 s w l r q e \ w h v [ [ ) ) [ [ ) ) ) [ [ ) ) ) [ [ ) ) [ ) ) [ ( ) ) [ [ ) & 3 8 6 : , 0 ' h e x j , 7 & 5 h j l v w h u v [ ) 5 h v h u y h g 5 h v h u y h g l q f o x g l q j 6 w d f n l q f o x g l q j ' d w d ( ( 3 5 2 0 x s w r . e \ w h v [ [ [ [ 8 q l t x h , ' 5 h v h u y h g / r z g h q v l w \ 0 6 9 docid15275 rev 14 23/83 stm8l101x1 stm8l101x2 stm8l101x3 memory and register map 32 note: 2 kbytes of data eeprom is only available on devices with 8 kbytes flash program memory. table 5. flash and ram boundary addresses memory area size start address end address ram 1.5 kbytes 0x00 0000 0x00 05ff flash program memory 2 kbytes 0x00 8000 0x00 87ff 4 kbytes 0x00 8000 0x00 8fff 8 kbytes 0x00 8000 0x00 9fff table 6. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pc_idr port c input pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 memory and register map stm8l101x1 stm8l101x2 stm8l101x3 24/83 docid15275 rev 14 table 7. general hardware register map address block register label register name reset status 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection register 0x00 0x00 5053 flash _dukr data eeprom unprotection register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0xx0 0x00 5055 to 0x00 509f reserved area (75 bytes) 0x00 50a0 itc-exti exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf external interrupt port select register 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 to 0x00 50af reserved area (8 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 to 0x00 50bf reserved area (14 bytes) 0x00 50c0 clk clk_ckdivr clock divider register 0x03 0x00 50c1 to 0x00 50c2 reserved area (2 bytes) 0x00 50c3 clk_pckenr peripheral clock gating register 0x00 0x00 50c4 reserved (1 byte) 0x00 50c5 clk_ccor configurable clock control register 0x00 0x00 50c6 to 0x00 50df reserved area (25 bytes) docid15275 rev 14 25/83 stm8l101x1 stm8l101x2 stm8l101x3 memory and register map 32 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr awu control/status register 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep control/status register 0x1f 0x00 50f4 to 0x00 51ff reserved area (268 bytes) 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 to 0x00 520f reserved area (11 bytes) 0x00 5210 i2c i2c_cr1 i2c control register 1 0x00 0x00 5211 i2c_cr2 i2c control register 2 0x00 0x00 5212 i2c_freqr i2c frequency register 0x00 0x00 5213 i2c_oarl i2c own address register low 0x00 0x00 5214 i2c_oarh i2c own address register high 0x00 0x00 5215 reserved area (1 byte) 0x00 5216 i2c_dr i2c data register 0x00 0x00 5217 i2c_sr1 i2c status register 1 0x00 0x00 5218 i2c_sr2 i2c status register 2 0x00 0x00 5219 i2c_sr3 i2c status register 3 0x00 0x00 521a i2c_itr i2c interrupt control register 0x00 0x00 521b i2c_ccrl i2c clock control register low 0x00 0x00 521c i2c_ccrh i2c clock control register high 0x00 0x00 521d i2c_triser i2c trise register 0x02 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l101x1 stm8l101x2 stm8l101x3 26/83 docid15275 rev 14 0x00 521e to 0x00 522f reserved area (18 bytes) 0x00 5230 usart usart_sr usart status register 0xc0 0x00 5231 usart_dr usart data register 0xxx 0x00 5232 usart_brr1 usart baud rate register 1 0x00 0x00 5233 usart_brr2 usart baud rate register 2 0x00 0x00 5234 usart_cr1 usart control register 1 0x00 0x00 5235 usart_cr2 usart control register 2 0x00 0x00 5236 usart_cr3 usart control register 3 0x00 0x00 5237 usart_cr4 usart control register 4 0x00 0x00 5238 to 0x00 524f reserved area (18 bytes) table 7. general hardware register map (continued) address block register label register name reset status docid15275 rev 14 27/83 stm8l101x1 stm8l101x2 stm8l101x3 memory and register map 32 0x00 5250 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_ier tim2 interrupt enable register 0x00 0x00 5255 tim2_sr1 tim2 status register 1 0x00 0x00 5256 tim2_sr2 tim2 status register 2 0x00 0x00 5257 tim2_egr tim2 event generation register 0x00 0x00 5258 tim2_ccmr1 tim2 capture/compare mode register 1 0x00 0x00 5259 tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 525a tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 525b tim2_cntrh tim2 counter high 0x00 0x00 525c tim2_cntrl tim2 counter low 0x00 0x00 525d tim2_pscr tim2 prescaler register 0x00 0x00 525e tim2_arrh tim2 auto-reload register high 0xff 0x00 525f tim2_arrl tim2 auto-reload register low 0xff 0x00 5260 tim2_ccr1h tim2 capture/compare register 1 high 0x00 0x00 5261 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5262 tim2_ccr2h tim2 capture/compare register 2 high 0x00 0x00 5263 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5264 tim2_bkr tim2 break register 0x00 0x00 5265 tim2_oisr tim2 output idle state register 0x00 0x00 5266 to 0x00 527f reserved area (26 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l101x1 stm8l101x2 stm8l101x3 28/83 docid15275 rev 14 0x00 5280 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_ier tim3 interrupt enable register 0x00 0x00 5285 tim3_sr1 tim3 status register 1 0x00 0x00 5286 tim3_sr2 tim3 status register 2 0x00 0x00 5287 tim3_egr tim3 event generation register 0x00 0x00 5288 tim3_ccmr1 tim3 capture/compare mode register 1 0x00 0x00 5289 tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 528a tim3_ccer1 tim3 capture/compare enable register 1 0x00 0x00 528b tim3_cntrh tim3 counter high 0x00 0x00 528c tim3_cntrl tim3 counter low 0x00 0x00 528d tim3_pscr tim3 prescaler register 0x00 0x00 528e tim3_arrh tim3 auto-reload register high 0xff 0x00 528f tim3_arrl tim3 auto-reload register low 0xff 0x00 5290 tim3_ccr1h tim3 capture/compare register 1 high 0x00 0x00 5291 tim3_ccr1l tim3 capture/compare register 1 low 0x00 0x00 5292 tim3_ccr2h tim3 capture/compare register 2 high 0x00 0x00 5293 tim3_ccr2l tim3 capture/compare register 2 low 0x00 0x00 5294 tim3_bkr tim3 break register 0x00 0x00 5295 tim3_oisr tim3 output idle state register 0x00 0x00 5296 to 0x00 52df reserved area (74 bytes) 0x00 52e0 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_ier tim4 interrupt enable register 0x00 0x00 52e4 tim4_sr1 tim4 status register 1 0x00 0x00 52e5 tim4_egr tim4 event generation register 0x00 0x00 52e6 tim4_cntr tim4 counter 0x00 0x00 52e7 tim4_pscr tim4 prescaler register 0x00 0x00 52e8 tim4_arr tim4 auto-reload register low 0xff table 7. general hardware register map (continued) address block register label register name reset status docid15275 rev 14 29/83 stm8l101x1 stm8l101x2 stm8l101x3 memory and register map 32 0x00 52e9 to 0x00 52fe reserved area (23 bytes) 0x00 52ff irtim ir_cr infra-red control register 0x00 0x00 5300 comp comp_cr comparator control register 0x00 0x00 5301 comp_csr comparator status register 0x00 0x00 5302 comp_ccs comparator channel selection register 0x00 table 8. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x80 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x05 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a cc condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cfg cfg_gcr global configuration register 0x00 0x00 7f61 0x00 7f6f reserved area (15 bytes) 0x00 7f70 itc-spr (1) itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l101x1 stm8l101x2 stm8l101x3 30/83 docid15275 rev 14 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 debug module control register 1 0x00 0x00 7f97 dm_cr2 debug module control register 2 0x00 0x00 7f98 dm_csr1 debug module control/status register 1 0x10 0x00 7f99 dm_csr2 debug module control/status register 2 0x00 0x00 7f9a dm_enfctr enable function register 0xff 1. refer to table 7: general hardware register map on page 24 (addresses 0x00 50a0 to 0x00 50a5) for a list of external interrupt registers. table 8. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status docid15275 rev 14 31/83 stm8l101x1 stm8l101x2 stm8l101x3 interrupt vector mapping 32 6 interrupt vector mapping table 9. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt ---- 0x00 8004 0 reserved 0x00 8008 1 flash eop/wr_pg_dis - - yes yes (1) 0x00 800c 2-3 reserved ---- 0x00 8010 -0x00 8017 4 awu auto wakeup from halt - yes yes yes (1) 0x00 8018 5 reserved ---- 0x00 801c 6 extib external interrupt port b yes yes yes yes 0x00 8020 7 extid external interrupt port d yes yes yes yes 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes 0x00 8044 16 reserved 0x00 8048 17 reserved ---- 0x00 804c -0x00 804f 18 comp comparators - - yes yes (1) 0x00 8050 19 tim2 update /overflow/trigger/break - - yes yes 0x00 8054 20 tim2 capture/compare - - yes yes 0x00 8058 21 tim3 update /overflow/break - - yes yes (1) 0x00 805c 22 tim3 capture/compare - - yes yes (1) 0x00 8060 23- 24 reserved ---- 0x00 8064- 0x00 806b 25 tim4 update /trigger - - yes yes (1) 0x00 806c 26 spi end of transfer yes yes yes yes (1) 0x00 8070 interrupt vector mapping stm8l101x1 stm8l101x2 stm8l101x3 32/83 docid15275 rev 14 27 usart transmission complete/transmit data register empty --yesyes (1) 0x00 8074 28 usart receive register data full/overrun/idle line detected/parity error --yesyes (1) 0x00 8078 29 i2c i2c interrupt (2) yes yes yes yes (1) 0x00 807c 1. in wfe mode, this interrupt is served if it has been previously enabled. after processing the interrupt, the processor goes back to wfe mode. refer to section wait for event (wfe) mode in the rm0013 reference manual. 2. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 9. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) vector address docid15275 rev 14 33/83 stm8l101x1 stm8l101x2 stm8l101x3 option bytes 34 7 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated row of the memory. all option bytes can be modified only in icp mode (with swim) by accessing the eeprom address. see table 10 for details on option byte addresses. refer to the stm8l flash programming manual (pm0054) and stm8 swim and debug manual (um0470) for information on swim programming procedures. table 10. option bytes addr. option name option byte no. option bits factory default setting 76543210 0x4800 read-out protection (rop) opt1 rop[7:0] 0x00 0x4807 - - must be programmed to 0x00 0x00 0x4802 ubc (user boot code size) opt2 ubc[7:0] 0x00 0x4803 datasize opt3 datasize[7:0] 0x00 0x4808 independent watchdog option opt4 [1:0] reserved iwdg _halt iwdg _hw 0x00 table 11. option byte description opt1 rop[7:0] memory readout protection (rop) 0xaa: enable readout protection (write access via swim protocol) refer to read-out protection section in the stm8l reference manual (rm0013) for details. opt2 ubc[7:0] size of the user boot code area 0x00: no ubc 0x01-0x02: ubc contains only the interrupt vectors. 0x03: page 0 and 1 reserved for the interrupt vectors. page 2 is available to store user boot code. memory is write protected ... 0x7f - page 0 to 126 reserved for ubc, memory is write protected refer to user boot area (ubc) section in the stm8l reference manual (rm0013) for more details. ubc[7] is forced to 0 internally by hw. option bytes stm8l101x1 stm8l101x2 stm8l101x3 34/83 docid15275 rev 14 caution: after a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. opt3 datasize[7:0] size of the data eeprom area 0x00: no data eeprom area (1) 0x01: 1 page reserved for data storage from 0x9fc0 to 0x9fff (1) 0x02: 2 pages reserved for data storage from 0x9f80 to 0x9fff (1) ... (1) 0x20: 32 pages reserved for data storage from 0x9800 to 0x9fff (1) refer to data eeprom (data) section in the stm8l reference manual (rm0013) for more details. datasize[7:6] are forced to 0 internal by hw. opt4 iwdg_hw: independent watchdog 0: independent watchdog activated by software 1: independent watchdog activated by hardware iwdg_halt: independent window watchdog reset on halt/active-halt 0: independent watchdog continues running in halt/active-halt mode 1: independent watchdog stopped in halt/active-halt mode 1. 0x00 is the only allowed value for 4 kbyte stm8l101xx devices. table 11. option byte description (continued) docid15275 rev 14 35/83 stm8l101x1 stm8l101x2 stm8l101x3 unique id 35 8 unique id stm8l101xx devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: ? for use as serial numbers ? for use as security keys to increase the code security in the program memory while using and combining this unique id with software cryptographic primitives and protocols before programming the internal memory ? to activate secure boot processes. table 12. unique id registers (96 bits) address content description unique id bits 7654 3 2 1 0 0x4925 x co-ordinate on the wafer u_id[7:0] 0x4926 u_id[15:8] 0x4927 y co-ordinate on the wafer u_id[23:16] 0x4928 u_id[31:24] 0x4929 wafer number u_id[39:32] 0x492a lot number u_id[47:40] 0x492b u_id[55:48] 0x492c u_id[63:56] 0x492d u_id[71:64] 0x492e u_id[79:72] 0x492f u_id[87:80] 0x4930 u_id[95:88] electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 36/83 docid15275 rev 14 9 electrical parameters 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). note: the values given at 85 c < t a 125 c are only valid for suffix 3 versions. data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 9.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3 v. they are given only as design guidelines and are not tested. 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . figure 9. pin loading conditions p & 3 4 - , 0 ) . 0 6 9 docid15275 rev 14 37/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 10. pin input voltage 9.2 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 0 6 9 6 ) . 3 4 - , 0 ) . table 13. voltage characteristics symbol ratings min max unit v dd - v ss external supply voltage -0.3 4.0 v v in input voltage on true open drain pins (pc0 and pc1) (1) 1. positive injection is not possible on these i/os. v in maximum must always be respected. i inj(pin) must never be exceeded. a negative injection is induced by v in electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 40/83 docid15275 rev 14 9.3.2 power-up / power-down operating conditions 9.3.3 supply current characteristics total current consumption the mcu is placed under the following conditions: ? all i/o pins in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled except if explicitly mentioned. subject to general operating conditions for v dd and t a . table 17. operating conditions at power-up / power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate 20 - 1300 s/v t temp reset release delay v dd rising - 1 - ms v por (1)(2) 1. data based on characterization results, not tested in production. 2. correct device reset during power on sequence is guaranteed when t vdd[max] is respected. external reset circuit is recommended to ensure correct device reset during power down, when v pdr < v dd < v dd[min] . power on reset threshold 1.35 - 1.65 (3) 3. tested in production. v v pdr (1)(2) power down reset threshold 1.40 - 1.60 v docid15275 rev 14 41/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 1. typical current consumption measured with code executed from flash. table 18. total current consumption in run mode (1) 1. based on characterization results, unless otherwise specified. symbol parameter conditions (2) 2. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc., f cpu =f master typ max (3) 3. maximum values are given for t a = ? 40 to 125 c. unit i dd (run) supply current in run mode (4) (5) 4. cpu executing typical data processing. 5. an approximate value of i dd(run) can be given by the following formula: i dd(run) = f master x 150 a/mhz +215 a. code executed from ram f master = 2 mhz 0.39 0.60 ma f master = 4 mhz 0.55 0.70 f master = 8 mhz 0.90 1.20 f master = 16 mhz 1.60 2.10 (6) 6. tested in production. code executed from flash f master = 2 mhz 0.55 0.70 f master = 4 mhz 0.88 1.80 f master = 8 mhz 1.50 2.50 f master = 16 mhz 2.70 3.50 figure 11. i dd(run) vs. v dd, f cpu = 2 mhz figure 12. i dd(run) vs. v dd , f cpu = 16 mhz ai17017 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd [v] i dd(run)hsi [ma] -40c 25c 85c 125c ai17018 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd [v] i dd(run)hsi [ma] -40c 25c 85c 125c electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 42/83 docid15275 rev 14 1. typical current consumption measured with code executed from flash. table 19. total current consumption in wait mode (1) 1. based on characterization results, unless otherwise specified. symbol parameter conditions typ max (2) 2. maximum values are given for t a = -40 to 125 c. unit i dd (wait) supply current in wait mode cpu not clocked, all peripherals off, hsi internal rc osc. f master = 2 mhz 245 400 a f master = 4 mhz 300 450 f master = 8 mhz 380 600 f master = 16 mhz 510 800 figure 13. i dd(wait) vs. v dd , f cpu = 2 mhz figure 14. i dd(wait) vs. v dd , f cpu = 16 mhz ai17015 0 50 100 150 200 250 300 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd [v] i dd(run)hsi [a] -40c 25c 85c 125c ai17016 200 250 300 350 400 450 500 550 600 1.6 2.1 2.6 3.1 3.6 v dd [v] i dd(wfi)hsi [a] -40c 25c 85c 125c docid15275 rev 14 43/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 figure 15. typ. i dd(halt) vs. v dd, f cpu = 2 mhz and 16 mhz 1. typical current consumption measured with code executed from flash. table 20. total current consumption and timing in halt and active-halt mode at v dd = 1.65 v to 3.6 v (1)(2) 1. t a = -40 to 125 c, no floating i/o, unless otherwise specified. 2. data based on characterization results, not tested in production. symbol parameter conditions typ max unit i dd(ah) supply current in active-halt mode lsi rc osc. (at 37 khz) t a = -40 c to 25 c 0.8 2 a t a = 55 c 1 2.5 a t a = 85 c 1.4 3.2 a t a = 105 c 2.9 7.5 a t a = 125 c 5.8 13 a i dd(wufah) supply current during wakeup time from active-halt mode 2-ma t wu(ah) (3) 3. measured from interrupt event to interrupt vector fetch. to get t wu for another cpu frequency use t wu (freq) = t wu (16 mhz) + 1.5 (t freq -t 16 mhz ). the first word of interrupt routine is fetched 5 cpu cycles after t wu . wakeup time from active- halt mode to run mode f cpu = 16 mhz 4 6.5 s i dd(halt) supply current in halt mode t a = -40 c to 25 c 0.35 1.2 (4) a t a = 55 c 0.6 1.8 a t a = 85 c 1 2.5 (4) 4. tested in production. a t a = 105 c 2.5 6.5 a t a = 125 c 5.4 12 (4) a i dd(wufh) supply current during wakeup time from halt mode 2-ma t wu(halt) (3) wakeup time from halt mode to run mode f cpu = 16 mhz 4 6.5 s ai17014b 0 1 2 3 4 5 6 7 1.6 2.1 2.6 3.1 3.6 v dd [v] i dd(halt) [a] -40c 25c 85c 125c electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 44/83 docid15275 rev 14 current consumption of on-chip peripherals measurement made for f master = from 2 mhz to 16 mhz table 21. peripheral current consumption symbol parameter typ. v dd = 3.0 v unit i dd(tim2) tim2 supply current (1) 1. data based on a differential i dd measurement between all peripherals off and a timer counter running at 16 mhz. the cpu is in wait mode in both cases. no ic/oc programmed, no i/o pin toggling. not tested in production. 9 a/mhz i dd(tim3) tim3 supply current (1) 9 i dd(tim4) tim4 timer supply current (1) 4 i dd(usart) usart supply current (2) 2. data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. the cpu is in wait mode in both cases. no i/o pin toggling. not tested in production. 7 i dd(spi) spi supply current (2) 4 i dd(i2c1) i2c supply current (2) 4 i dd(comp) comparator supply current (2) 20 a docid15275 rev 14 45/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 9.3.4 clock and timing characteristics internal clock sources subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) figure 16. typical hsi frequency vs. v dd table 22. hsi oscillator characteristics (1) 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency v dd = 3.0 v - 16 - mhz acc hsi accuracy of hsi oscillator (factory calibrated) v dd = 3.0 v, t a = 25 c -1 - 1 % v dd = 3.0 v, -10 c t a 85 c -2.5 (2) -2 (2) % v dd = 3.0 v, -10 c t a 125 c -4.5 (2) -2 (2) % v dd = 3.0 v, 0 c t a 55 c -1.5 (2) 2. data based on characterization results, not tested in production. - 1.5 (2) % v dd = 3.0 v, -10 c t a 70 c -2 (2) -2 (2) % 1.65 v v dd 3.6 v, -40 c t a 125 c -4.5 (2) -3 (2) % i dd(hsi) hsi oscillator power consumption - 70 100 (2) a ai17013 15 15.2 15.4 15.6 15.8 16 16.2 16.4 16.6 16.8 17 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] hsi frequency [mhz] -40c 25c 85c 125c electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 46/83 docid15275 rev 14 figure 17. typical hsi accuracy vs. temperature, v dd = 3 v figure 18. typical hsi accuracy vs. temperature, v dd = 1.65 v to 3.6 v low speed internal rc oscillator (lsi) table 23. lsi oscillator characteristics (1) 1. v dd = 1.65 v to 3.6 v, t a = -40 to 125 c unless otherwise specified. symbol parameter conditions min typ max unit f lsi frequency 26 38 56 khz f drift(lsi) lsi oscillator frequency drift (2) 2. for each individual part, this value is the frequency drift from the initial measured frequency . 0 c t a 85 c -12 - 11 % ai17021 -5.0% -4.5% -4.0% -3.5% -3.0% -2.5% -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 temperature ( c) rc accuracy 3v min 3v typical 3v max ai17019 -5.0% -4.5% -4.0% -3.5% -3.0% -2.5% -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 temperature ( c) rc accuracy min 1.65v-3.6v max 1.65v-3.6v 3v typical docid15275 rev 14 47/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 figure 19. typical lsi rc frequency vs. v dd 9.3.5 memory characteristics t a = -40 to 125 c unless otherwise specified. ai17012b 25 27 29 31 33 35 37 39 41 43 45 1.62.12.63.13.6 v dd [v] lsi frequency [mhz] -40c 25c 85c 125c table 24. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by characterization, not tested in production. flash memory halt mode (or reset) 1.4 - - v table 25. flash program memory symbol parameter conditions min typ max (1) unit v dd operating voltage (all modes, read/write/erase) f master = 16 mhz 1.65 - 3.6 v t prog programming time for 1- or 64-byte (block) erase/write cycles (on programmed byte) -6-ms programming time for 1- to 64-byte (block) write cycles (on erased byte) -3-ms i prog programming/ erasing consumption t a =+25 c, v dd = 3.0 v - 0.7 - ma t a =+25 c, v dd = 1.8 v - - electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 48/83 docid15275 rev 14 9.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. t ret data retention (program memory) after 10k erase/write cycles at t a = +85 c t ret = 55 c 20 (1) -- years data retention (data memory) after 10k erase/write cycles at t a = +85 c t ret = 55 c 20 (1) -- data retention (data memory) after 300k erase/write cycles at t a = +125 c t ret = 85 c 1 (1) -- n rw erase/write cycles (program memory) see notes (1)(2) 10 (1) -- kcycles erase/write cycles (data memory) see notes (1)(3) 300 (1)(4) -- 1. data based on characterization results, not tested in production. 2. retention guaranteed after cycling is 10 years at 55 c. 3. retention guaranteed after cycling is 1 year at 55 c. 4. data based on characterization performed on the whole data memory (2 kbytes). table 25. flash program memory (continued) symbol parameter conditions min typ max (1) unit table 26. i/o static characteristics (1) symbol parameter conditions min typ max unit v il input low level voltage (2) standard i/os v ss -0.3 - 0.3 x v dd v true open drain i/os v ss -0.3 - 0.3 x v dd v ih input high level voltage (2) standard i/os 0.70 x v dd -v dd +0.3 v true open drain i/os v dd < 2 v 0.70 x v dd - 5.2 true open drain i/os v dd 2 v 5.5 v hys schmitt trigger voltage hysteresis (3) standard i/os - 200 - mv true open drain i/os - 250 - i lkg input leakage current (4) v ss v in v dd standard i/os - - 50 (5) na v ss v in v dd true open drain i/os - - 200 (5) v ss v in v dd pa0 with high sink led driver capability - - 200 (5) docid15275 rev 14 49/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 figure 20. typical v il and v ih vs. v dd (high sink i/os) figure 21. typical v il and v ih vs. v dd (true open drain i/os) r pu weak pull-up equivalent resistor (6) v in = v ss 30 45 60 k c io (7) i/o pin capacitance - 5 - pf 1. v dd = 3.0 v, t a = -40 to 85 c unless otherwise specified. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. not tested in production. 6. r pu pull-up equivalent resistor based on a resistive transistor (corresponding i pu current characteristics described in figure 22 ). 7. data guaranteed by design, not tested in production. table 26. i/o static characteristics (1) (continued) symbol parameter conditions min typ max unit ai17011 0 0.5 1 1.5 2 2.5 3 1.6 2.1 2.6 3.1 3.6 v dd [v] v il and v ih [v] -40c 25c 85c 125c 0 0.5 1 1.5 2 2.5 3 1.6 2.1 2.6 3.1 3.6 v dd [v] v il and v ih [v] -40c 25c 85c 125c ai17010 0 0.5 1 1.5 2 2.5 3 1.62.12.63.13.6 v dd [v] v il and v ih [v] -40c 25c 85c 125c electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 50/83 docid15275 rev 14 figure 22. typical pull-up resistance r pu vs. v dd with v in =v ss figure 23. typical pull-up current i pu vs. v dd with v in =v ss ai17009 30 35 40 45 50 55 60 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] pull-up resistance [k ] -40c 25c 85c 125c ai17008 0 20 40 60 80 100 120 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] pull-up current [a] -40c 25c 85c 125c docid15275 rev 14 51/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 output driving current subject to general operating conditions for v dd and t a unless otherwise specified. table 27. output driving current (high sink ports) i/o type symbol parameter conditions min max unit standard v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 14 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +2 ma, v dd = 3.0 v - 0.45 v i io = +2 ma, v dd = 1.8 v - 0.45 v i io = +10 ma, v dd = 3.0 v - 1.2 v v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in table 14 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin i io = -2 ma, v dd = 3.0 v v dd -0.45 - v i io = -1 ma, v dd = 1.8 v v dd -0.45 - v i io = -10 ma, v dd = 3.0 v v dd -1.2 - v table 28. output driving current (true open drain ports) i/o type symbol parameter conditions min max unit open drain v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 14 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +3 ma, v dd = 3.0 v - 0.45 v i io = +1 ma, v dd = 1.8 v - 0.45 v table 29. output driving current (pa0 with high sink led driver capability) i/o type symbol parameter conditions min max unit ir v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 14 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +20 ma, v dd = 2.0 v - 0.9 v electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 52/83 docid15275 rev 14 figure 24. typ. v ol at v dd = 3.0 v (high sink ports) figure 25. typ. v ol at v dd = 1.8 v (high sink ports) ai17005 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.1 0.2 0.3 0.4 0.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 125c ai17004 figure 26. typ. v ol at v dd = 3.0 v (true open drain ports) figure 27. typ. v ol at v dd = 1.8 v (true open drain ports) ai17003 0 0.1 0.2 0.3 0.4 0.5 0123456 i ol [ma] v ol [v] -40c 25c 85c 125c ai17002 0 0.1 0.2 0.3 0.4 0.5 00.511.522.53 i ol [ma] v ol [v] -40c 25c 85c 125c figure 28. typ. v dd - v oh at v dd = 3.0 v (high sink ports) figure 29. typ. v dd - v oh at v dd = 1.8 v (high sink ports) ai17001 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012141618202224 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c ai17000 0 0.1 0.2 0.3 0.4 0123456 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c docid15275 rev 14 53/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 nrst pin the nrst pin input driver is cmos. a permanent pull-up is present. r pu(nrst) has the same value as r pu (see table 26 on page 48 ). subject to general operating conditions for v dd and t a unless otherwise specified. figure 30. typical nrst pull-up resistance r pu vs. v dd table 30. nrst pin characteristics symbol parameter conditions min typ (1) max unit v il(nrst) nrst input low level voltage (1) 1. data based on characterization results, not tested in production. v ss - 0.8 v v ih(nrst) nrst input high level voltage (1) 1.4 - v dd v ol(nrst) nrst output low level voltage i ol = 2 ma - - v dd -0.8 r pu(nrst) nrst pull-up equivalent resistor (2) 2. the r pu pull-up equivalent resistor is based on a resistive transistor ( figure 30 ). corresponding i pu current characteristics are described in figure 31 . 30 45 60 k v f(nrst) nrst input filtered pulse (3) 3. data guaranteed by design, not tested in production. - - 50 ns t op(nrst) nrst output pulse width 20 - - ns v nf(nrst) nrst input not filtered pulse (3) 300 - - ns ai17007 30 35 40 45 50 55 60 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] pull-up resistance [k ] -40c 25c 85c 125c electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 54/83 docid15275 rev 14 figure 31. typical nrst pull-up current i pu vs. v dd the reset network shown in figure 32 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in table 30 . otherwise the reset is not taken into account internally. for power consumption- sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. if the nrst signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. the minimum recommended capacity is 10 nf. figure 32. recommended nrst pin configuration 1. correct device reset during power on sequence is guaranteed when t vdd[max] is respected. 2. external reset circuit is recommended to ensure correct device reset during power down, when v pdr < v dd < v dd[min] . ai17006 0 20 40 60 80 100 120 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] pull-up current [a] -40c 25c 85c 125c m ) ( ; 7 ( 5 1 $ / 5 ( 6 ( 7 & , 5 & 8 , 7 6 7 0 / & i l t e r 2 0 5 6 $ $ ) . 4 % 2 . ! , 2 % 3 % 4 5 6 7 , 1 0 6 9 docid15275 rev 14 55/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 9.3.7 communication interfaces serial peripheral interface (spi) unless otherwise specified, the parameters given in table 31 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions summarized in section 9.3.1 . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 31. spi characteristics symbol parameter conditions (1) min max unit f sck 1/t c(sck) spi clock frequency master mode 0 8 mhz slave mode 0 8 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 30 ns t su(nss) (2) nss setup time slave mode 4 x t master - t h(nss) (2) nss hold time slave mode 80 - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f master = 8 mhz, f sck = 4 mhz 105 145 t su(mi) (2) t su(si) (2) data input setup time master mode 30 - slave mode 3 - t h(mi) (2) t h(si) (2) data input hold time master mode 15 - slave mode 0 - t a(so) (2)(3) data output access time slave mode - 3x t master t dis(so) (2)(4) data output disable time slave mode 30 - t v(so) (2) data output valid time slave mode (after enable edge) - 60 t v(mo) (2) data output valid time master mode (after enable edge) -20 t h(so) (2) data output hold time slave mode (after enable edge) 15 - t h(mo) (2) master mode (after enable edge) 1- 1. parameters are given by selecting 10-mhz i/o output frequency. 2. values based on design simulation and/or characterization results, and not tested in production. 3. min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in hi-z. electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 56/83 docid15275 rev 14 figure 33. spi timing diagram - slave mode and cpha = 0 figure 34. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input docid15275 rev 14 57/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 figure 35. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 58/83 docid15275 rev 14 inter ic control interface (i2c) subject to general operating conditions for v dd , f master , and t a unless otherwise specified. the stm8l i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). note: for speeds around 200 khz, achieved speed can have 5% tolerance for other speed ranges, achieved speed can have 2% tolerance the above variations depend on the accuracy of the external components used. table 32. i2c characteristics symbol parameter standard mode i2c fast mode i2c (1) 1. f sck must be at least 8 mhz to achieve max fast i 2 c speed (400 khz). unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. -0 (4) 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl ). 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf docid15275 rev 14 59/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 figure 36. typical application with i2c bus and timing diagram 1) 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd 9.3.8 comparator characteristics 5 ( 3 ( $ 7 ( ' 6 7 $ 5 7 6 7 $ 5 7 6 7 2 3 6 7 $ 5 7 w i 6 ' $ w u 6 ' $ w v x 6 ' $ w k 6 ' $ w i 6 & / w u 6 & / w z 6 & / / w z 6 & / + w k 6 7 $ w v x 6 7 2 w v x 6 7 $ w z 6 7 2 6 7 $ 6 ' $ 6 & / n 7 6 ' $ 6 7 0 / 6 & / 9 ' ' 7 7 9 ' ' n 7 , & % 8 6 0 6 9 table 33. comparator characteristics symbol parameter conditions min (1) typ max (1) unit v in(comp_ref) comparator external reference -0.1 - v dd -1.25 v v in comparator input voltage range -0.25 - v dd +0.25 v v offset (2) comparator offset error - - 20 mv t start startup time (after bias_en) - - 3 (1) s i dd(comp) analog comparator consumption - - 25 (1) a analog comparator consumption during power-down --60 (1) na t propag (2) comparator propagation delay 100-mv input step with 5-mv overdrive, input rise time = 1 ns --2 (1) s 1. data guaranteed by design, not tested in production. 2. the comparator accuracy depends on the environment. in particular, the following cases may reduce the accuracy of the comparator and must be avoided: - negative injection current on the i/os close to the comparator inputs - switching on i/os close to the comparator inputs - negative injection current on not used comparator input. - switching with a high dv/dt on not used comparator input. these phenomena are even more critical when a big external serial resistor is added on the inputs. electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 60/83 docid15275 rev 14 9.3.9 emc characteristics susceptibility tests are performed on a sample basis during product characterization. functional ems (electromagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? esd : electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 34. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance lqfp32, v dd = 3.3 v 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance lqfp32, v dd = 3.3 v, f hsi 3b lqfp32, v dd = 3.3 v, f hsi /2 4a docid15275 rev 14 61/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/3 which specifies the board and the loading of each pin. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. table 35. emi data (1) 1. not tested in production. symbol parameter conditions monitored frequency band max vs. unit 16 mhz s emi peak level v dd = 3.6 v, t a = +25 c, lqfp32 conforming to iec61967-2 0.1 mhz to 30 mhz -3 db v 30 mhz to 130 mhz -6 130 mhz to 1 ghz -5 sae emi level 1 - table 36. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) 500 electrical parameters stm8l101x1 stm8l101x2 stm8l101x3 62/83 docid15275 rev 14 static latch-up ? lu : 2 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. 9.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 16: general operating conditions on page 39 . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ? p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. ? p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh) *i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 37. electrical sensitivities symbol parameter class lu static latch-up class ii docid15275 rev 14 63/83 stm8l101x1 stm8l101x2 stm8l101x3 electrical parameters 63 table 38. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51-2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 60 c/w thermal resistance junction-ambient ufqfpn 32 - 5 x 5 mm 25 c/w thermal resistance junction-ambient ufqfpn 28 - 4 x 4 mm 80 c/w thermal resistance junction-ambient ufqfpn 20 - 3 x 3 mm - 0.6 mm 102 c/w thermal resistance junction-ambient tssop 20 110 c/w package characteristics stm8l101x1 stm8l101x2 stm8l101x3 64/83 docid15275 rev 14 10 package characteristics 10.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack? is an st trademark. docid15275 rev 14 65/83 stm8l101x1 stm8l101x2 stm8l101x3 package characteristics 75 10.2 package mechanical data figure 37. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5) 1. drawing is not to scale. 2. all leads/pads should be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. ! / " ? - % package characteristics stm8l101x1 stm8l101x2 stm8l101x3 66/83 docid15275 rev 14 figure 38. ufqfpn32 recommended footprint 1. dimensions are in millimeters. table 39. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data dim. mm inches (1) min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.0500 0 0.0008 0.0020 a3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d2 - 3.500 - - 0.1378 - e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd 0.080 0.0031 number of pins n32 1. values in inches are converted from mm and rounded to 4 decimal digits. $ % b ) 3 b 9 docid15275 rev 14 67/83 stm8l101x1 stm8l101x2 stm8l101x3 package characteristics 75 figure 39. lqfp32 - 32-pin low profile quad flat package outline (7 x 7) 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e package characteristics stm8l101x1 stm8l101x2 stm8l101x3 68/83 docid15275 rev 14 figure 40. lqfp32 recommended footprint table 40. lqfp32- 32-pin low profile quad flat package (7x7), package mechanical data dim. mm inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - 0.100 - - 0.0039 - number of pins n32 1. values in inches are converted from mm and rounded to 4 decimal digits. 6 ? & 0 ? 6 docid15275 rev 14 69/83 stm8l101x1 stm8l101x2 stm8l101x3 package characteristics 75 figure 41. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4 mm) 4 e b 3 e a t i n g 0 l a n e ! ! # o x ? 0 i n c o r n e r , , 2 o 4 y p $ e t a i l : $ $ % % 0 i n ) $ 3 e a t i n g 0 l a n e " ! $ e t a i l : ! " ? - % ? 6 table 41. ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data dim. mm inches (1) min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0 0.020 0.050 0 0.0008 0.002 a3 - 0.152 - - 0.0060 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 d - 4.000 - - 0.1575 - e - 4.000 - - 0.1575 - e - 0.500 - - 0.0197 - l1 0.250 0.350 0.450 0.0098 0.0138 0.0177 l2 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - 0.080 - - 0.0031 - number of pins n28 package characteristics stm8l101x1 stm8l101x2 stm8l101x3 70/83 docid15275 rev 14 figure 42. ufqfpn28 recommended footprint 1. values in inches are converted from mm and rounded to 4 decimal digits. ! " ? & 0 ? 6 docid15275 rev 14 71/83 stm8l101x1 stm8l101x2 stm8l101x3 package characteristics 75 figure 43. ufqfpn20 - 20-lead ultra thin fine pitch quad flat package outline (3x3 mm) 1. drawing is not to scale. ! ! ? - % ? 6 $ e b e % ! ! d d d , , ! , , $ % 4 / 0 6 ) % 7 3 ) $ % 6 ) % 7 " / 4 4 / - 6 ) % 7 0 i n , table 42. ufqfpn20 - 20-lead ultra thin fine pitch quad flat package (3 x 3 mm) mechanical data symbol millimeters inches (1) min typ max min typ max d - 3.000 - - 0.1181 - e - 3.000 - - 0.1181 - a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.0060 - e - 0.500 - - 0.0197 - l1 0.500 0.550 0.600 0.0197 0.0217 0.0236 l2 0.300 0.350 0.400 0.0118 0.0138 0.0157 l3 - 0.375 - - 0.0148 - package characteristics stm8l101x1 stm8l101x2 stm8l101x3 72/83 docid15275 rev 14 figure 44. ufqfpn20 recommended footprint 1. dimensions are in millimeters l4 - 0.200 - - 0.0079 - l5 - 0.150 - - 0.0059 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 ddd - 0.050 - - 0.0020 - 1. values in inches are rounded to 4 decimal digits table 42. ufqfpn20 - 20-lead ultra thin fine pitch quad flat package (3 x 3 mm) mechanical data (continued) symbol millimeters inches (1) min typ max min typ max ! ! ? & 0 ? 6 docid15275 rev 14 73/83 stm8l101x1 stm8l101x2 stm8l101x3 package characteristics 75 figure 45. tssop20 - 20-lead thin shrink small package outline 1. drawing is not to scale. 9 ! ? - % ? 6 # c , % % $ ! ! k e b ! , a a a 3 % ! 4 ) . ' 0 , ! . % # ' ! 5 ' % 0 , ! . % m m 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . table 43. tssop20 - 20-lead thin shrink small package mechanical data dim. mm inches (1) min typ max min typ max a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 cp - - 0.100 - - 0.0039 c 0.090 - 0.200 0.0035 - 0.0079 d (2) 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 (3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - 0.1693 0.0256 - l 0.450 0.600 0.750 0.1693 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0 - 8 0 - 8 package characteristics stm8l101x1 stm8l101x2 stm8l101x3 74/83 docid15275 rev 14 figure 46. tssop20 recommended footprint aaa - - 0.100 - - 0.0039 number of pins 20 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 3. dimension ?e1? does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25mm per side. table 43. tssop20 - 20-lead thin shrink small package mechanical data (continued) dim. mm inches (1) min typ max min typ max 9 ! ? & 0 ? 6 docid15275 rev 14 75/83 stm8l101x1 stm8l101x2 stm8l101x3 device ordering information 75 11 device ordering information figure 47. stm8l101xx ordering information scheme 1. for a list of available options (e.g. memory size, package) and order-able part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. 3 4 - , & 5 ! 4 2 0 r o d u c t c l a s s 3 4 - m i c r o c o n t r o l l e r 0 i n c o u n t + p i n s ' p i n s & p i n s 0 a c k a g e 5 5 & 1 & 0 . 4 , 1 & 0 0 4 3 3 / 0 % x a m p l e 3 u b f a m i l y t y p e s u b f a m i l y & a m i l y t y p e , , o w p o w e r 4 e m p e r a t u r e r a n g e ? # t o ? # ? # t o ? # 0 r o g r a m m e m o r y s i z e + b y t e s + b y t e s + b y t e s # / - 0 ? 2 % & a v a i l a b i l i t y o n 5 & 1 & 0 . a n d 5 & 1 & 0 . ! # / - 0 ? 2 % & a v a i l a b l e " l a n k # / - 0 ? 2 % & n o t a v a i l a b l e 3 h i p p i n g 4 2 4 a p e a n d r e e l " l a n k 4 r a y stm8 development tools stm8l101x1 stm8l101x2 stm8l101x3 76/83 docid15275 rev 14 12 stm8 development tools development tools for the stm8 microcontrollers include the full-featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environment with high-level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 emulation and in-circuit debugging tools the stice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. in addition, stm8 application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full featured emulators from stmicroelectronics. it offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features ? occurrence and time profiling and code coverage (new features) ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in-circuit debugging/programming via swim protocol ? 8-bit probe analyzer ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. docid15275 rev 14 77/83 stm8l101x1 stm8l101x2 stm8l101x3 stm8 development tools 77 12.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st visual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8. a free version that outputs up to 32 kbytes of code is available. 12.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com . this package includes: st visual develop ? full-featured integrated development environment from st, featuring ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulation features for stice such as code profiling and coverage st visual programmer (stvp) ? easy-to-use, unlimited graphical interface allowing read, write and verify of your stm8 microcontroller flash program memory, data eeprom and option bytes. stvp also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 c and assembly toolchains control of c and assembly toolchains is seamlessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: ? cosmic c compiler for stm8 ? one free version that outputs up to 32 kbytes of code is available. for more information, see www.cosmic-software.com. ? raisonance c compiler for stm8 ? one free version that outputs up to 32 kbytes of code. for more information, see www.raisonance.com. ? stm8 assembler linker ? free assembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. 12.3 programming tools during the development cycle, stice provides in-circuit programming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family. revision history stm8l101x1 stm8l101x2 stm8l101x3 78/83 docid15275 rev 14 13 revision history table 44. document revision history date revision changes 19-dec-2008 1 initial release. 22-apr-2009 2 added tssop28 package modified packages on first page compx_out pins removed added figure 6: 28-pin tssop package pinout on page 17 modified section 9: electrical parameters on page 36 . updated ubc[7:0] description in section 7: option bytes . updated low power current consumption on cover page. updated table 13: voltage characteristics , table 20: total current consumption and timing in halt and active-halt mode at vdd = 1.65 v to 3.6 v , table 26: i/o static characteristics , table 30: nrst pin characteristics , and section 9.3.9: emc characteristics . updated pa1/nrst, pc0 and pc1 in table 4: stm8l101xx pin description . added ecc feature. changed internal rc frequency to 38 khz. updated electrical characteristics in table 16 , table 18 , table 19 , table 20 , table 22 , table 23 , and table 26 . 24-apr-2009 3 corrected title on cover page. changed vfqfpn32 to wfqfpn32 and updated table 39: ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . updated table 13 , table 26 , and table 33 . 14-may-2009 4 replaced wfqfpn20 3 x 3 mm 0.8 mm package by ufqfpn20 3 x 3 mm 0.6 mm package (first page, table 16: general operating conditions on page 39 , table 38: thermal characteristics on page 63 , section 10.2: package mechanical data on page 67 ) added one ufqfpn20 version with comp_ref modified figure 40: lqfp32 recommended footprint (1) on page 69 added i prog values in table 25: flash program memory on page 47 updated table 31: spi characteristics on page 55 15-may-2009 5 added stm8l101f3u6atr part number in section 4: pin description on page 14 and in figure 47: stm8l101xx ordering information scheme on page 74 docid15275 rev 14 79/83 stm8l101x1 stm8l101x2 stm8l101x3 revision history 82 12-jun-2009 6 removed tssop28 package modified consumption value on first page added beep_csr (address 00 50f3h) in table 7: general hardware register map on page 24 tim2_pscrl replaced with tim2_pscr and clk_pcken replaced with clk_pckenr in table 7: general hardware register map on page 24 added graphs in section 9: electrical parameters on page 36 added t wu (ah) and t wu (halt) max values in table 20: total current consumption and timing in halt and active-halt mode at vdd = 1.65 v to 3.6 v on page 43 modified table 20: total current consumption and timing in halt and active-halt mode at vdd = 1.65 v to 3.6 v on page 43 updated table 22: hsi oscillator characteristics on page 45 , table 23: lsi oscillator characteristics on page 46 and table 24: ram and hardware registers on page 47 modified table 27: output driving current (high sink ports) on page 51 removed note 1 in table 37: electrical sensitivities on page 62 added note to table 39: ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data on page 67 and table 41: ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data on page 70 table 44. document revision history (continued) date revision changes revision history stm8l101x1 stm8l101x2 stm8l101x3 80/83 docid15275 rev 14 07-sep-2009 7 added STM8L101F2U6ATR, stm8l101g2u6atr and stm8l101g3u6atr part numbers modified section 2: description on page 8 . modified table 2: stm8l101xx device feature summary on page 8 (flash) modified figure 1: stm8l101xx device block diagram on page 9 modified section 3.5: memory on page 11 added note below figure 2: standard 20-pin ufqfpn package pinout on page 14 and figure 5: standard 28-pin ufqfpn package pinout on page 16 added figure 6: 28-pin ufqfpn package pinout for stm8l101g3u6atr and stm8l101g2u6atr part numbers on page 17 modified reset values for px_idr registers in table 6: i/o port hardware register map on page 23 added section 6: interrupt vector mapping on page 31 modified opt numbers in section 7: option bytes modified opt2 in table 10: option bytes added section 8: unique id on page 35 tim_ir pin replaced with ir_tim pin modified table 20: total current consumption and timing in halt and active-halt mode at vdd = 1.65 v to 3.6 v on page 43 modified figure 15: typ. idd(halt) vs. vdd, fcpu = 2 mhz and 16 mhz on page 43 and figure 19: typical lsi rc frequency vs. vdd on page 47 modified table 27: output driving current (high sink ports) on page 51 updated table 29: output driving current (pa0 with high sink led driver capability) on page 51 modified : functional ems (electromagnetic susceptibility) on page 60 modified conditions in table 35: emi data on page 61 added note to figure 37: ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5) on page 67 modified figure 41: ufqfpn28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4) (1) on page 70 added figure 44: ufqfpn20 recommended footprint (1) on page 71 added figure 46: tssop20 recommended footprint (1) on page 72 cmp replaced with comp table 44. document revision history (continued) date revision changes docid15275 rev 14 81/83 stm8l101x1 stm8l101x2 stm8l101x3 revision history 82 29-nov-2009 8 modified status of the document (datasheet instead of preliminary data) replaced wfqfpn32 with ufqfpn32 and wfqfpn28 with ufqfpn28. modified title of the reference manual mentioned in section 2: description on page 8 added references to ?low-density? in section 2: description on page 8 , section 3.5: memory on page 11 and in figure 8: memory map on page 22 modified figure 8: memory map on page 22 (unique id are added) table 7: general hardware register map on page 24 : modified reserved areas and ir block replaced with irtim block modified t temp in table 17: operating conditions at power-up / power-down on page 40 modified table 23: lsi oscillator characteristics on page 46 modified table 25: flash program memory on page 47 (t prog ) modified table 16: general operating conditions on page 39 and table 38: thermal characteristics on page 63 modified section 13: revision history on page 78 18-jun-2010 9 modified introduction and description modified one reserved area (0x00 5055 to 0x00 509f) in table 7: general hardware register map modified table 4: stm8l101xx pin description : modified note 2 and removed ?wpu? for pc0 and pc1 removed one note to table 22: hsi oscillator characteristics on page 45 modified first paragraph in section : nrst pin modified opt3 description in table 11: option byte description added note 5 to table 18: total current consumption in run mode modified v esd(cdm) in table 36: esd absolute maximum ratings on page 61 modified figure 36: typical application with i2c bus and timing diagram 1) on page 59 modified comp_ref availability information in figure 47: stm8l101xx ordering information scheme on page 75 modified section 12.2: software tools on page 78 21-jul-2010 10 modified table 3: legend/abbreviation for table 4 on page 19 and table 4: stm8l101xx pin description on page 19 (for pa0, pa1, pb0 and pb4) modified table 13: voltage characteristics on page 37 and table 14: current characteristics on page 38 modified v ih in table 26: i/o static characteristics on page 48 added notes below ufqfpn32 package table 44. document revision history (continued) date revision changes revision history stm8l101x1 stm8l101x2 stm8l101x3 82/83 docid15275 rev 14 14-oct-2010 11 added stm8l101f1 devices: modified table 1: device summary on page 1 , table 2: stm8l101xx device feature summary on page 8 and table 5: flash and ram boundary addresses on page 23 modified warning below figure 3 on page 15 and below table 4: stm8l101xx pin description on page 19 modified figure 47: stm8l101xx ordering information scheme on page 75 modified text above figure 32: recommended nrst pin configuration on page 54 modified figure 32 on page 54 02-aug-2013 12 added ?the ram content is preserved? in halt mode section 3.6: low power modes reformatted figure 2: standard 20-pin ufqfpn package pinout , figure 3: 20-pin ufqfpn package pinout for stm8l101f1u6atr, STM8L101F2U6ATR and stm8l101f3u6atr part numbers , figure 4: 20-pin tssop package pinout , figure 4: 20-pin tssop package pinout , figure 5: standard 28-pin ufqfpn package pinout , figure 6: 28-pin ufqfpn package pinout for stm8l101g3u6atr and stm8l101g2u6atr part numbers and figure 7: 32-pin package pinout corrected nrst/pa1 pin od output capability in table 4: stm8l101xx pin description and corrected note 2. and 4. added note ?slope control of all gpio can be programmed except...? in table 4: stm8l101xx pin description added note under table 5: flash and ram boundary addresses replaced um0320 with um0470 in section 7: option bytes updated opt2 and opt3 in table 10: option bytes added additional note 2. references in table 22: hsi oscillator characteristics added note 2. under table 17: operating conditions at power-up / power-down and under figure 32: recommended nrst pin configuration corrected ?sck output? in figure 35: spi timing diagram - master mode(1) added top view in figure 43: ufqfpn20 3 x 3 mm 0.6 mm package outline repositioned the package layout and footprint for all packages. replaced ?standard ports? with ?high sink ports? replaced ?timx_trig? with ?timx_etr? replaced all ?"data guaranteed, each individual device tested in production? notes with ?tested in production? 31-mar-2014 13 updated l3 value on table 42 , added note 2) and 3) on table 43 18-dec-2014 14 updated: ? figure 43: ufqfpn20 - 20-lead ultra thin fine pitch quad flat package outline (3x3 mm) , ? table 42: ufqfpn20 - 20-lead ultra thin fine pitch quad flat package (3 x 3 mm) mechanical data . table 44. document revision history (continued) date revision changes docid15275 rev 14 83/83 stm8l101x1 stm8l101x2 stm8l101x3 83 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved |
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